1. Field of the Invention
The present invention relates to silicon-on-insulator (SOI) wafer device isolation technology, and more particularly to a method of fabricating a modified SOI structure having a buried semiconductor layer.
2. Description of the Related Art
PN junction isolation between adjacent devices on a bulk silicon substrate is used in the manufacture of silicon integrated circuits, but is not suitable for high voltage applications since junction breakdowns occur at supply voltages of about ±30 V under appropriate doping level and dimensions. Furthermore, PN junction isolation between the adjacent devices is not effective in a radioactive environment due to transient photocurrent caused by gamma rays at the PN junction.
To overcome the above noted disadvantages of conventional PN junction isolation techniques, silicon on insulator (SOI) technologies have been developed. In SOI technologies, a device is completely encompassed with an insulating material in place of the normal PN junction. Circuits manufactured on a SOI substrate have advantages in that the overall chip size is reduced, the fabrication process and resulting structure are simplified compared to circuits manufactured in a bulk silicon substrate, and parasitic capacitances between the devices and the bulk silicon substrate are reduced to achieve high speed operation thereof.
Commonly known techniques for obtaining SOI structures include silicon-on-sapphire (SOS) which allows heteroepitaxial silicon layer to be grown on sapphire, separation by implanted oxygen (SIMOX) which creates a buried silicon oxide layer by implanting oxygen ions into a silicon substrate and annealing the substrate, and bonding SOI by which at least one wafer having an insulating layer thereon is bonded to another wafer.
Despite the advantages described above, metal-oxide-semiconductor (MOS) field effect transistors (FETs) formed on a SOI wafer have a problem in that a floating body effect occurs because a buried oxide layer isolates the body of the transistor from the silicon substrate. When an NMOS transistor is operated, holes generated by impact ionization are accumulated in the electrically floating body, thereby raising a potential of the body. The increased body potential reduces the threshold voltage of the device. The increased body potential causes an undesirable kink effect in drain current vs. voltage curves of the NMOS transistor, and induces operation of a parasitic bipolar transistor, thereby leading to an instability of gate control over source-drain current.
FIG. 1 is a cross-section of a MOS transistor formed on a SOI wafer having a SiGe layer buried in the body region of the transistor thereon. Referring to FIG. 1, an insulating layer 20 is formed on a substrate 10. A silicon layer 32, a SiGe layer 34, and a silicon device layer 36 are formed in sequence on the insulating layer 20. A gate electrode 42 is formed on the device layer 36 with a gate insulating layer 40 interposed therebetween. A spacer 44 is formed on a sidewall of the gate electrode 42. A source region 46 and a drain region 48, both of which are self-aligned to the spacer 44 and doped with impurities, are formed over the device layer 36, the SiGe layer 34, and the silicon layer 32.
In the configuration of the transistor of FIG. 1, since the valence band of the SiGe material exists closer to a Fermi level than that of the silicon material, since the SiGe material has a band gap narrower than the silicon material, a potential barrier for holes is lowered at a junction of the SiGe layer 34 and the silicon device layer 36. Furthermore, when a drain voltage is applied to the MOS device, electrons cause impact ionization at the drain region 48. The holes generated by the impact ionization move to the SiGe layer 34 having a lowered potential barrier for holes and then to the source region 46 through the SiGe layer 34, thereby suppressing the floating body effect.
However, since the MOS transistor of FIG. 1 has a partially depleted structure, it has relatively low transconductance and low switching speed.